The present invention relates to integrated circuit devices and, more particularly, to redundancy circuits for memory devices and methods of repairing defective cells.
As the cell density of semiconductor memory devices, such as dynamic random access memories (DRAMs), increases, the interval between bitlines thereof generally decreases. As a result, bitline coupling noise may be significantly increased during sensing of memory cell data. A twist bitline scheme has been proposed to reduce bitline coupling noise.
In the twist bitline design, a bitline BL and a complementary bitline {overscore (BL)} are typically twisted at regular intervals. By adequately controlling the layout arrangement between an odd column and an even column, a bitline coupling noise generated by a bitline BL and a complementary bitline {overscore (BL)} in a column may be offset by a bitline coupling noise received from bitlines in an adjacent column. Consequently, the bitline coupling noises in the two adjacent columns may be reduced or even eliminated.
When a defective cell is detected in a memory cell array having this twist bitline design, the defective cell is typically repaired by replacement with spare cell (or a redundancy cell). Consequently, a semiconductor production yield may be improved using a redundancy cell. In the twist bitline design having twisted bitlines, memory cells connected to one wordline generally have different data scrambles according to their locations.
FIG. 1 illustrates a data scrambling that may occur after repairs in a twist bitline design and a folded bitline design. As shown in FIG. 1, first bitline and complementary bitline BL0 and {overscore (BL0)} form a twist bitline design (scheme), and second bitline and complementary bitline BL1 and {overscore (BL1)} form a folded bitline design (scheme). In FIG. 1, memory cells are defined by the first bitline and complementary bitline BL0 and {overscore (BL0)}, and the second bitline and complementary bitline BL1 and {overscore (BL1)} and first through fourth wordlines WL0 through WL3 that cross the bitlines BL0, {overscore (BL0)}, BL1, and {overscore (BL1)}. For the device of FIG. 1, when a data pattern (value) stored in a memory cell is 1, the data pattern is represented as T(True). When a data pattern stored in a memory cell is 0, the data pattern is represented as C(Complement).
It is assumed for purposes of this description that the memory cells connected to the first through fourth wordlines WL0 through WL3 in the twist bitline structure store a “TCCT” data pattern. If these memory cells are defective, and the first through fourth wordlines WL0 through WL3 are replaced by first through fourth spare wordlines SWL0 through SWL3, spare cells connected to the first through fourth spare wordlines SWL0 through SWL3 store a “CTTC” data pattern, because the bitlines are twisted. In other words, data scrambling occurs. In this case, during final defective cell screening after primary defective cell repairing, defective cells may not be screened or normal cells may have a high risk of being detected as defective cells based on lack of information about the data scrambling.
In contrast, for the folded bitline scheme, if the memory cells connected to the first through fourth wordlines WL0 through WL3 are defective and replaced by the spare cells connected to the first through fourth spare wordlines SWL0 through SWL3, the spare cells store a TCCT data pattern the same as the TCCT data pattern stored by the memory cells connected to the first through fourth wordlines WL0 through WL3.
Thus, to repair a defective cell in a twist bitline scheme, if bitlines are twisted once, a spare wordline for repairing a wordline connected to the defective cell (hereinafter, referred to as a defective wordline) typically must exist on each side of a place where the bitlines are twisted, so that data are stored in spare cells connected to the spare wordline to have the same data scramble as that of the defective cell in the folded bitline scheme.
However, to repair a defective wordline with a spare wordline in the twist bitline scheme, an address fuse cutting portion for repairing an address corresponding to the defective wordline with an address corresponding to the spare wordline typically must be installed in the spare wordline. In other words, each spare wordline typically requires an address fuse cutting portion. Because the address fuse cutting portion generally occupies a large area of a layout of a memory device. A chip size of the memory device generally proportionally increases as a number of memory cells having different data scrambles increases.